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DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
22
Output Frequency / DAC Frequency
0.000
0.125
0.250
0.375
0.500
0.000
0.125
0.250
0.375
0.500
Spur
Frequency
/
DAC
Frequency
IF 3fDAC/4
IF fDAC/4
IF + fDAC/4
IF fDAC/2
Output IF
Figure 23. Location of Clock Mixing Spurs vs IF for 4
y Mode
The offset between wanted and spurious signals is maximized at low IFs (< fDAC/8) and at fDAC × 3/16,
fDAC
× 5/16, and fDAC × 7/16. For example, with fDATA = 100 MSPS and 4× interpolation, operating with
IF = fDAC × 5/16 = 125 MHz results in spurious signals at offsets of ±50 MHz from the wanted signal.
Figure 24a shows the amplitude of each spurious signal as a function of IF in external-clock mode. The
dominant spurious signal is IF fDAC/2. The amplitudes of the IF + fDAC/4 and IF fDAC/4 are the next-highest
spurious signals and are approximately at the same amplitude. Finally, at IF frequencies greater than 100 MHz,
small spurious signals at IF fDAC × 3/4 are measurable.
Figure 24b shows the amplitude of each spurious signal as a function of IF in PLL clock mode. Generating the
DAC clock with the onboard PLL/VCO increases the IF fDAC/2 by 3 dB. The amplitude of the IF ± fDAC/4 and
IF fDAC × 3/4 remain at about the same level as in the external-clock mode.
a. External Clock Mode
b. PLL Mode
70
60
50
40
30
20
10
0
50
100
150
200
fsig Output Frequency MHz
Amplitude
of
Spurs
dBc
IF FDAC/2
IF + FDAC/4
IF 3FDAC/4
IF FDAC/4
70
60
50
40
30
20
10
0
50
100
150
200
fsig Output Frequency MHz
Amplitude
of
Spurs
dBc
IF FDAC/2
IF + FDAC/4
IF 3FDAC/4
IF FDAC/4
Figure 24. External Clock Mode and PLL Mode
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